M6MGD137W34DKT renesas lsis 134,217,728 - bit (8,388,608 - word by 16 - bit) cmos flash memory & 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos mobileram stacked - m mcp (micro multi chip package) rev.1.0.48a_bezc 1 preliminary notice: this is not a final specification. some parametric limits are subject to change. pin configuration (top view) the M6MGD137W34DKT is a stacked micro multi chip package (s - m mcp) that contents 128m - bit flash memory and 32m - bit mobileram in a 52 - pin tsop for lead free use. 128m - bit flash memory is a 8,388,608 words, single power supply and high performance non - volatile memory fabricated by cmos technology for the peripheral circuit and dinor iv (divided bit - line nor iv) architecture for the memory cell. all memory blocks are locked and can not be programmed or erased, when f - wp# is low. using software lock release function, program or erase operation can be executed. 32m - bit mobileram is a 2,097,152 words high density ram fabricated by cmos technology for the peripheral circuit and dram cell for the memory array. the interface is compatible to an asynchronous sram. the cells are automatically refreshed and the refresh control is not required for system. the device also has the partial block refresh scheme and the power down mode by writing the command. the M6MGD137W34DKT is suitable for a high performance cellular phone and a mobile pc that are required to be small mounting area, weight and small power dissipation. outline 52ptj - a mobile communication products 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a15 a14 a13 a12 a11 a10 a9 a8 a19 m - ce # we # f - rp # f - wp # nc nc a20 a18 a17 a7 a6 a5 a4 a3 a16 m - ub # gnd m - lb # dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 fm - vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe # gnd 28 27 f - ce 1# a0 25 26 a2 a1 10.49 mm 10.79 mm a21 f - ce2 # description features access time flash 70ns (max.) mobileram 80ns (max.) supply voltage fm - vcc = 2.7 ~ 3.0v ambient temperature ta= - 40 ~ 85 c package 52pin tsop(type - ii), lead pitch 0.4mm outer - lead finishing: sn - cu application fm - vcc : common vcc for flash / mobileram gnd :common gnd for flash / mobileram a0 - a20 : common address for flash / mobileram a21 :address for flash dq0 - dq15 :data i/o f - ce1# :flash chip enable1 f - ce2# :flash chip enable2 m - ce# : mobileram chip enable oe# :output enable for flash/ mobileram we# :write enable for flash/ mobileram f - wp# : write protect for flash f - rp# :reset power down for flash m - lb# :lower byte control for mobileram m - ub # :upper byte control for mobileram M6MGD137W34DKT
M6MGD137W34DKT renesas lsis 134,217,728 - bit (8,388,608 - word by 16 - bit) cmos flash memory & 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos mobileram stacked - m mcp (micro multi chip package) rev.1.0.48a_bezc 2 preliminary notice: this is not a final specification. some parametric limits are subject to change. capacitance mcp block diagram a0 to a21 a0 to a21 f-wp# f-rp# we# oe# m-ub# m-lb# dq0 to dq15 128mbit dinor iv flash memory 32mbit mobileram fm-vcc gnd f-ce1# f-ce2# a0 to a20 m-ce# min. typ. max. pf pf pf pf cout output capacitance dq15-dq0 34 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter input capacitance cin a21-a0, oe#, we#, f-wp#, f-rp#, m- ce#, m-lb#, m-ub#, f-ce1#, f-ce2# 26 note: in the 128m - bit dinor(iv) flash memory lower 64mbit is selected by f - ce1#= ? l ? and upper 64mbit is done by f - ce2#= ? l ? . never select each chip at the same time. in the data sheet there are ? vcc ? s which mean ? fm - vcc ? (common vcc for flash / mobileram ). in the flash memory part they mean a21, oe# and we# a re f - a21, f - oe# and f - we#. in the mobileram part ub# , lb#, oe# and we# are m - ub# , m - lb#, m - oe# and m - we#, respectively.
M6MGD137W34DKT renesas lsis 134,217,728 - bit (8,388,608 - word by 16 - bit) cmos flash memory & 33,554,432 - bit (2,097,152 - word by 16 - bit) cmos mobileram stacked - m mcp (micro multi chip package) these materials are intended as a reference to assist our custom ers in the selection of the renesas technology corporation product best suited to the customer's ap plication; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage , or infringement of any third - party's rights, originating in the use of any product data, diag rams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents infor mation on products at the time of publication of these materials , and are subject to change by renesas technology corporation without notice due to product improvemen ts or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product informati on before purchasing a product listed herein. the information described here may contain technical inaccuracie s or typographical errors. renesas technology corporation assumes no responsibility for any damage , liability, or other loss rising from these inaccuracies or err ors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page ( http://www.renesas.com ). when using any or all of the information contained in these mate rials, including product data, diagrams, charts, programs, and a lgorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage , liability or other loss resulting from the information contain ed herein. renesas technology corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. please conta ct renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, su ch as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese ex port control restrictions, they must be exported under a license from the japanese government and cannot be imported into a coun try other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan an d/or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials o r the products contained therein. renesas technology corporation puts the maximum effort into making semi conductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage.remember to give due co nsideration to safety when making your circuit designs, with app ropriate measures such as (i) placement of substitutive, auxilia ry circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials keep safety first in your circuit designs! rej03c0124 ? 2003 renesas technology corp. new publication, effective april 2003. specifications subject to change without notice nippon bldg.,6 - 2, otemachi 2 - chome, chiyoda - ku ,tokyo,100 - 0004 japan
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